ARM cortex-m programmer's model : Program Status Registers (PSR)

Ref: ARM v8m Arch

core-registers (M3)

core-registers (M7)

APSR : Application Program Status Register

Table 2.4. APSR bit assignments

Bits	Name	Function
[31]	N	Negative flag.
[30]	Z	Zero flag.
[29]	C	Carry or borrow flag.
[28]	V	Overflow flag.
[27]	Q	DSP overflow and saturation flag.
[26:20]	-	Reserved.
[19:16]	GE[3:0]	Greater than or Equal flags. See SEL for more information.
[15:0]	-	Reserved.

IPSR : interrupt Program Status Register

Table 2.5. IPSR bit assignments

Bits	Name	Function
[31:9]	-	Reserved.
[8:0]	ISR_NUMBER	This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = HardFault 4 = MemManage 5 = BusFault 6 = UsageFault 7-10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 . . . n+15 = IRQ(n-1)[a]. See Exception types for more information.
[a] The number of interrupts, n, is implementation-defined, in the range 1-240.

EPSR: Execution Program Status Register

Table 2.6. EPSR bit assignments

Bits	Name	Function
[31:27]	-	Reserved.
[26:25], [15:10]	ICI/IT	Indicates the interrupted position of a continuable instruction, see Interruptible-continuable instructions, or the execution state of an IT instruction, see IT.
[24]	T	Thumb state bit, see Thumb state.