AAPCS
procedure call standard for ARM architecture
Ref:
hard-fault-handler.pdf
Ref:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/Cihcbadd.html
可以先看 HFSR 是哪一種錯誤
Hard Fault Status Register
Use the Hard Fault Status Register (HFSR) to obtain information about events that activate the Hard Fault handler.
The register address, access type, and Reset state are:
- Address
0xE000ED2C
- Access
Read/write-one-to-clear
- Reset state
0x00000000
The HFSR is a write-clear register. This means that writing a 1 to a bit clears that bit.
Figure 8.19 shows the fields of the Hard Fault Status Register.
Table 8.24 describes the fields of the Hard Fault Status Register.
Table 8.24. Hard Fault Status Register bit assignments
| Bits | Field | Function |
|---|
| [31] | DEBUGEVT |
This bit is set if there is a fault related to debug.
This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.
|
| [30] | FORCED | Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled.The Hard Fault handler then has to read the other fault status registers to determine cause. |
| [29:2] | - | Reserved. |
| [1] | VECTTBL | This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. |
| [0] | - | Reserved. |
--
如果是 configurable fault
Configurable Fault Status Registers
Use the three Configurable Fault Status Registers to obtain information about local faults. These registers include:
The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.
The register addresses, access types, and Reset states are:
- Address
0xE000ED28 Memory Manage Fault Status Register
0xE000ED29 Bus Fault Status Register
0xE000ED2A Usage Fault Status Register
- Access
Read/write-one-to-clear
- Reset state
0x00000000
Figure 8.15 shows the fields of the Configurable Fault Status Registers.
Memory Manage Fault Status Register
The flags in the Memory Manage Fault Status Register indicate the cause of memory access faults.
The register address, access type, and Reset state are:
- Address
0xE000ED28
- Access
Read/write-one-to-clear
- Reset state
0x00000000
Figure 8.16 shows the fields of the Memory Manage Fault Status Register.
Table 8.21 describes the fields of the Memory Manage Fault Status Register.
Table 8.21. Memory Manage Fault Status Register bit assignments
| Bits | Field | Function |
|---|
| [7] | MMARVALID |
Memory Manage Address Register (MMAR) address valid flag:
1 = valid fault address in MMAR. A later-arriving fault, such as a bus fault, can clear a memory manage fault.
0 = no valid fault address in MMAR.
If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten.
|
| [4] | MSTKERR | Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. The MMAR is not written. |
| [3] | MUNSTKERR | Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The MMAR is not written. |
| [1] | DACCVIOL | Data access violation flag. Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error loads MMAR with the address of the attempted access. |
| [0] | IACCVIOL | Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written. |
Bus Fault Status Register
The flags in the Bus Fault Status Register indicate the cause of bus access faults.
The register address, access type, and Reset state are:
- Address
0xE000ED29
- Access
Read/write-one-to-clear
- Reset state
0x00000000
Figure 8.17 shows the fields of the Bus Fault Status Register.
Table 8.22 describes the fields of the Bus Fault Status Register.
Table 8.22. Bus Fault Status Register bit assignments
| Bits | Field | Function |
|---|
| [7] | BFARVALID |
This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later.
If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.
|
| [6:5] | - | Reserved. |
| [4] | STKERR | Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. The BFAR is not written. |
| [3] | UNSTKERR | Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The BFAR is not written. |
| [2] | IMPRECISERR | Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. The BFAR is not written. |
| [1] | PRECISERR | Precise data bus error return. |
| [0] | IBUSERR |
Instruction bus error flag:
1 = instruction bus error
0 = no instruction bus error.
The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. The BFAR is not written.
|
Usage Fault Status Register
The flags in the Usage Fault Status Register indicate the following errors:
illegal combination of EPSR and instruction
illegal PC load
illegal processor state
instruction decode error
attempt to use a coprocessor instruction
illegal unaligned access.
The register address, access type, and Reset state are:
- Address
0xE000ED2B
- Access
Read/write clear
- Reset state
0x00000000
Figure 8.18 shows the fields of the Usage Fault Status Register.
Table 8.23 describes the fields of the Usage Fault Status Register.
Table 8.23. Usage Fault Status Register bit assignments
| Bits | Field | Function |
|---|
| [9] | DIVBYZERO | When DIV_0_TRP (see Configuration Control Register) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a quotient of 0. |
| [8] | UNALIGNED | When UNALIGN_TRP is enabled (see Configuration Control Register), and there is an attempt to make an unaligned memory access, then this fault occurs.Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP. |
| [7:4] | - | Reserved. |
| [3] | NOCP | Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. |
| [2] | INVPC | Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. |
| [1] | INVSTATE | Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. Return PC points to faulting instruction, with the invalid state. |
| [0] | UNDEFINSTR | The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. |
--
Configuration Control Register
Use the Configuration Control Register to:
enable NMI, Hard Fault and FAULTMASK to ignore bus fault
trap divide by zero, and unaligned accesses
enable user access to the Software Trigger Exception Register
control entry to Thread Mode.
The register address, access type, and Reset state are:
- Address
0xE000ED14
- Access
Read/write
- Reset state
0x00000000
Figure 8.12 shows the fields of the Configuration Control Register.
Table 8.18 describes the fields of the Configuration Control Register.
Table 8.18. Configuration Control Register bit assignments
| Bits | Field | Function |
|---|
| [9] | STKALIGN |
1 = on exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return.
0 = only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.
|
| [8] | BFHFNMIGN | When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored – you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them. |
| [4] | DIV_0_TRP | Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault Status Register. |
| [3] | UNALIGN_TRP | Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED, see Usage Fault Status Register. |
| [1] | USERSETMPEND | If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer. |
| [0] | NONEBASETHRDENA | When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value. |
- SHCSR
System Handler Control and State Register
Use the System Handler Control and State Register to:
enable or disable the system handlers
determine the pending status of bus fault, mem manage fault, and SVC
determine the active status of the system handlers.
If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault.
The register address, access type, and Reset state are:
- Address
0xE000ED24
- Access
Read/write
- Reset state
0x00000000
Figure 8.14 shows the fields of the System Handler and State Control Register.
Table 8.20 describes the fields of the System Handler Control Register.
Table 8.20. System Handler Control and State Register bit assignments
| Bits | Field | Function |
|---|
| [31:19] | - | Reserved |
| [18] | USGFAULTENA | Set to 0 to disable, else 1 for enabled. |
| [17] | BUSFAULTENA | Set to 0 to disable, else 1 for enabled. |
| [16] | MEMFAULTENA | Set to 0 to disable, else 1 for enabled. |
| [15] | SVCALLPENDED | Reads as 1 if SVCall is pended. |
| [14] | BUSFAULTPENDED |
Reads as 1 if BusFault is pended.
|
| [13] | MEMFAULTPENDED | Reads as 1 if MemManage is pended. |
| [12] | USGFAULTPENDED | Read as 1 if usage fault is pended |
| [11] | SYSTICKACT | Reads as 1 if SysTick is active. |
| [10] | PENDSVACT | Reads as 1 if PendSV is active. |
| [9] | - | Reserved |
| [8] | MONITORACT | Reads as 1 if the Monitor is active. |
| [7] | SVCALLACT | Reads as 1 if SVCall is active. |
| [6:4] | - | Reserved |
| [3] | USGFAULTACT | Reads as 1 if UsageFault is active. |
| [2] | - | Reserved |
| [1] | BUSFAULTACT | Reads as 1 if BusFault is active. |
| [0] | MEMFAULTACT | Reads as 1 if MemManage is active. |
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