ARM cortex-m7 register : system control block

ARM : cortex-m7 system control block



CCR :

Table 4.12. Summary of the system control block registers

Address	Name	Type	Required privilege	Reset value	Description
0xE000E008	ACTLR	RW	Privileged	0x00000000	Auxiliary Control Register
0xE000ED00	CPUID	RO	Privileged	0x410FC270[a]	CPUID Base Register
0xE000ED04	ICSR	RW[b]	Privileged	0x00000000	Interrupt Control and State Register
0xE000ED08	VTOR	RW	Privileged	Unknown	Vector Table Offset Register
0xE000ED0C	AIRCR	RW[b]	Privileged	0xFA050000	Application Interrupt and Reset Control Register
0xE000ED10	SCR	RW	Privileged	0x00000000	System Control Register
0xE000ED14	CCR	RW	Privileged	0x00000200[a]	Configuration and Control Register
0xE000ED18	SHPR1	RW	Privileged	0x00000000	System Handler Priority Register 1
0xE000ED1C	SHPR2	RW	Privileged	0x00000000	System Handler Priority Register 2
0xE000ED20	SHPR3	RW	Privileged	0x00000000	System Handler Priority Register 3
0xE000ED24	SHCRS	RW	Privileged	0x00000000	System Handler Control and State Register
0xE000ED28	CFSR	RW	Privileged	0x00000000	Configurable Fault Status Register
0xE000ED28	MMSR[c]	RW	Privileged	0x00	MemManage Fault Status Register
0xE000ED29	BFSR[c]	RW	Privileged	0x00	BusFault Status Register
0xE000ED2A	UFSR[c]	RW	Privileged	0x0000	UsageFault Status Register
0xE000ED2C	HFSR	RW	Privileged	0x00000000	HardFault Status Register
0xE000ED34	MMAR	RW	Privileged	Unknown	MemManage Fault Address Register
0xE000ED38	BFAR	RW	Privileged	Unknown	BusFault Address Register
0xE000ED3C	AFSR	RAZ/WI	Privileged	-	Auxiliary Fault Status Register not implemented

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CCR 

Table 4.20. CCR bit assignments

Bits	Name	Type	Function
[31:19]	-	-	Reserved.
[18]	BP	RO	Always reads-as-one. It indicates branch prediction is enabled.
[17]	IC	RW	Enables L1 instruction cache. This bit is optional: 0 L1 instruction cache disabled. 1 L1 instruction cache enabled.
[16]	DC	RW	Enables L1data cache. This bit is optional: 0 L1 data cache disabled. 1 L1 data cache enabled.
[15:10]	-	-	Reserved.
[9]	STKALIGN	RO	Always reads-as-one. It indicates stack alignment on exception entry is 8-byte aligned. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
[8]	BFHFNMIGN	RW	Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the hard fault, NMI, and FAULTMASK escalated handlers: 0 Data bus faults caused by load and store instructions cause a lock-up. 1 Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.
[7:5]	-	-	Reserved.
[4]	DIV_0_TRP	RW	Enables faulting or halting when the processor executes an SDIV or UDIVinstruction with a divisor of 0: 0 Do not trap divide by 0. 1 Trap divide by 0. When this bit is set to 0, a divide by zero returns a quotient of 0.
[3]	UNALIGN_TRP	RW	Enables unaligned access traps: 0 Do not trap unaligned halfword and word accesses. 1 Trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a UsageFault. Unaligned LDM, STM, LDRD, and STRDinstructions always fault irrespective of whether UNALIGN_TRP is set to 1.
[2]	-	-	Reserved.
[1]	USERSETMPEND	RW	Enables unprivileged software access to the STIR, see Software Trigger Interrupt Register: 0 Disable. 1 Enable.
[0]	NONBASETHRDENA	RW	Indicates how the processor enters Thread mode: 0 Processor can enter Thread mode only when no exception is active. 1 Processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception return.